1. Field of the Invention
The invention relates generally to semiconductor memory devices and, more particularly, relates to a semiconductor memory device in which data is serially read and an operating method thereof.
2. Description of the Background Art
FIG. 4 is a block diagram showing one example of the configuration of a dual port memory. The dual port memory includes a random accessible memory cell array arranged in a matrix and a serial accessible serial memory cell array, and has been often used recently, for example, as a memory for video processing.
In FIG. 4, each of four memory cell arrays 1a, 1b, 1c, 1d includes a plurality of memory cells arranged in a matrix having a plurality of rows and a plurality of columns. External address signals A0-An are applied to an address buffer 2. A row decoder 3 receives an address signal from the address buffer 2 and selects one row in each of the memory cell arrays 1a, 1b, 1c, 1d. A column decoder 4 receives an address signal from the address buffer 2 and selects one column in each of the memory cell arrays 1a, 1b, 1c, 1d. The data in the four memory cells selected by the row decoder 3 and the column decoder 4 is respectively supplied to data input-output terminals r1-r4 through an I/O switch circuit 5 and an input/output circuit 6. Data D0-D3 of 4 bits supplied to the data input-output terminals r1-r4 is supplied to a memory cell selected by the row decoder 3 and the column decoder 4 through the input-output circuit 6 and the I/O switch circuit 5.
Each of serial memory cell arrays 8a, 8b, 8c, 8d includes a plurality of memory cells arranged in one row. Data of one row is transferred by a transfer circuit 7 between each of the serial memory cell arrays 8a-8d and each of the memory cell arrays 1a-1d. A serial selector 9 receives an address signal from the address buffer 2 and indicates a start address in each of the serial memory cell arrays 8a-8d. Then, an external clock signal SC supplied to an input terminal 14 is converted into an internal signal iSC in a clock generator 13. The serial selector 9 sequentially selects one bit in each of the serial memory cell arrays 8a-8d in response to the internal signal iSC. An I/O switch circuit 10 and an input-output circuit 11 transfer serial input-output data SD0-SD3 between the serial memory cell arrays 8a-8d and the data input-output terminals s1-s4.
A timing generator 12 generates each kind of timing signals for controlling the operation of each portion in response to an externally applied row address strobe signal RAS, a column address strobe signal CAS, a data transfer/output enable signal DT/OE and a write per bit/write enable signal WB/WE. The clock generator 13 generates an internal clock signal iSC and transfer signals .phi.1, .phi.1, .phi.2, .phi.2 in response to the external clock signal SC.
FIG. 5 is a circuit diagram showing the structure of the main portion of the dual port memory in FIG. 4.
A plurality of bit line pairs BL, BL are arranged in the memory cell array 1a. A plurality of word lines WL are arranged to cross those bit line pairs BL, BL. A memory cell MC is provided at a cross-over point of a word line WL and a bit line BL or a bit line BL. The plurality of word lines WL are connected to a row decoder 3. A sense amplifier SA is connected to each bit line pair BL, BL. Each sense amplifier SA is connected to data input-output line pair DIO, DIO through N channel MOS transistors Q1, Q2. A column selecting signal is supplied to the gates of the transistors Q1, Q2 from a column decoder 4. The transistors Q1, Q2 and the data input-output line pair DIO, DIO constitute an I/O switch circuit 5.
A static type memory cell SMC including inverters G1, G2 is connected to each bit line pair BL, BL through N channel MOS transistors Q3, Q4. A data transfer signal DT is applied to the gates of the transistors Q3, Q4. A plurality of pairs of transistors Q3, Q4 constitute a transfer circuit 7. A plurality of memory cells SMC constitute a serial memory cell array 8a.
Each memory cell SMC is connected to a data input-output line pair SIO, SIO through N channel MOS transistors Q5, Q6. A selecting signal is applied to the gates of the transistors Q5, Q6 from a serial selector 9. A plurality of pairs of transistors Q5, Q6 and the data input-output line pair SIO, SIO constitute an I/O switch circuit 10.
The read operation of the memory cell array 1a is described. Any one of the plurality of word lines WL is selected by the row decoder 3. Data is read to respectively corresponding bit line pair BL, BL from the plurality of memory cells MC connected to the selected word line WL. The data read into each bit line pair BL, BL is amplified by the sense amplifier SA. Any one pair of the plurality of pairs of transistors Q1, Q2 is selected by the column decoder 4. As a result, the selected pair of transistors Q1, Q2 turn on, so that the data read into the corresponding bit line pair BL, BL is transferred to the data input-output line pair DIO, DIO.
The read operation of the serial memory cell array 8a will now be described. One pair of the plurality of pairs of transistors Q5, Q6 is selected by the serial selector 9. The selected transistors Q5, Q6 turn on, so that the data stored in the corresponding memory cell SMC is transferred to the data input-output line pair SIO, SIO. The serial selector 9 serially selects a plurality of pairs of transistors Q5, Q6 in response to an internal clock signal iSC supplied from the clock generator 13.
In the dual port memory of FIG. 4, picture information can be stored in the memory cell arrays 1a-1d from a CRT controller and so on through the data input-output terminals r1-r4. The picture information stored the memory cell arrays 1a-1d is transferred to the serial memory cell arrays 8a-8d by the serial transfer circuit 7. The picture information transferred to the serial memory cell arrays 8a-8d is serially, and externally supplied through the data input-output terminals s1-s4.
As the serial memory cell arrays 8a-8d can operate in an access time and a cycle time of about 30 nsec, data can be obtained at higher speed compared with the memory cell arrays 1a-1d having an access time and a cycle time of about 200 nsec.
While writing of data in the memory cell arrays 1a-1d is being effected, data can be read asynchronously from the serial memory cell arrays 8a-8d. Therefore, data can be obtained without a read stop period and at high speed. They are therefore widely used as a memory for video processing.
FIG. 6 is a circuit diagram showing the structure of the input-output circuit 11 shown in FIG. 4.
The input-output circuit of FIG. 6 includes amplifiers 101, 107, a first transfer circuit 102, a second transfer circuit 104, a first latch circuit 103, a second latch circuit 105, an output circuit 106 and inverters G7, G8. The inverter G8 and the output circuit 106 constitute a main amplifier.
At the time of reading data, the amplifier 101 amplifies the data of the input-output line pair SIO, SIO at high speed. At the time of writing data, the amplifier 107 amplifies the data SDi supplied to the data input-output terminal si at high speed and applies the amplified data to the data input-output line pair SIO, SIO, where i represents 0, 1, 2, 3.
The first transfer circuit 102 includes P channel MOS transistors Q11, Q12 and N channel MOS transistors Q13, Q14. Transfer signals .phi.1, .phi.1 are supplied to the gates of the transistors Q11, Q14, respectively. The transfer signals .phi.1 and .phi.1 are complementary to each other. The first latch circuit 103 includes .inverters G3, G4. The second transfer circuit 104 includes P channel MOS transistors Q15, Q16 and N channel MOS transistors Q17, Q18. Transfer signals .phi.2, .phi.2 are supplied to the gates of the transistors Q15, Q18, respectively. The transfer signals .phi.2, .phi.2 are complementary to each other. The second latch circuit 105 includes inverters G5, G6. The output circuit 106 includes N channel MOS transistors Q19, Q20.
The operation of reading data in the input-output circuit of FIG. 6 will now be described with reference to the waveform diagrams in FIGS. 7 and 8.
A description is made here of a case in which the data read from the n-th address of the serial memory cell arrays 8a-8d is externally supplied as output. The data read from the n-th address of the serial access memory is held in the first latch circuit 103. Referring to FIG. 7, when the external clock signal SC rises to an H level, at first, the transfer signal .phi.2 rises to an H level. The second transfer circuit 104 turns on, and the data held in the first latch circuit 103 is transferred to the second latch circuit 105. As a result the data held in the second latch circuit 105 is amplified by the output circuit 106 and supplied to the data input-output terminal si.
The access time tSCA from the time the external clock signal SC rises to an H level to the time the data SDi is supplied to the data input-output terminal si is at most 5 to 10 nsec. The time (previous data hold time) tSOH from the time the external clock signal SC rises to an H level to the time the data which has been outputted in the previous cycle starts changing is at most 0-5 nsec.
The transfer signal .phi.2 falls to an L level when a fixed period of time has passed after it attained an H level. After .phi.2 has completely attained an L level, the transfer signal .phi.1 rises to an H level. The first transfer circuit 102 turns on, and the data read from the (n+1)-th address in preparation for a read operation of the next cycle is transferred to the first latch circuit 103 through the data input-output line pair SIO, SIO and the amplifier 101.
In the next cycle, after the data held in the first latch circuit 103 is transferred to the second latch circuit 105, the data read from the (n+2)-th address is transferred to the first latch circuit 103. In this way, a look ahead system is employed. As a result, the access time tSCA becomes a sufficiently short value.
As stated above, while the access time tSCA becomes short enough in accordance with the conventional input-output circuit shown in FIG. 6, there is a problem that the previous data hold time tSOH becomes too short. The input-output circuit of FIG. 6 is a complete edge-triggered circuit. The data in the previous cycle changes and the data in the next cycle is outputted in response to the rising edge of the external clock signal SC from an L level to an H level.
In a practical system in which such a dual port memory is used, data is often inputted at a rising edge from an L level to an H level of the external clock signal SC. Therefore, the previous data hold time tSOH of 5-10 nsec must be ensured as a standard of the device.
However, when the previous data hold time tSOH is made longer, as shown in FIG. 8, the access time tSCA also becomes longer. The maximum value of the access time tSCA in the standard of the device is determined as 20-25 nsec. In this way, the time period from the time the external clock signal SC is supplied to the time the transfer signal .phi.2 shown in FIGS. 7 and 8 rises to an H level involves a problem if it is too short or too long and must be in an extremely narrow range.
If the time period from the time the external clock signal SC is applied to the time the transfer signal .phi.2 rises is delayed, an optimum previous data hold time tSOH and access time tSCA can be obtained. After the transfer signal .phi.2 falls, however, a transfer signal .phi.1 must be supplied in preparation for a read operation in the next cycle. When an external clock signal SC in the next cycle is supplied in the period from the time .phi.1 rises to an H level to the time it falls to an L level, a malfunction is caused. That is, the time at which the transfer signal .phi.1 falls is a limit of the minimum cycle time tSCC. The standard of the minimum value of the cycle time tSCC is about 30 nsec.
In this way, there is a problem that the minimum value of the cycle time tSCC becomes longer if the previous data hold time tSOH and the access time tSCA are made longer.